Portfolio
Detailed project documentation covering requirements, architecture, implementation, verification, debugging, and results.
A modular SystemVerilog processor built around a shared 256-bit tri-state bus, with dedicated matrix and integer ALUs, a multi-cycle execution engine, and automated Vivado/XSim verification.
Educational FPGA platform designed to give engineering students practical experience with digital design, embedded systems, and hardware/software integration. The project combined reusable SystemVerilog modules, AXI-based peripherals, guided laboratory procedures, technical documentation, and hardware demonstrations on a Zynq-7000 development board.
A living Astro and GitHub Pages project I use to learn AI-assisted development, VS Code, HTML, CSS, Git, debugging, accessibility, and iterative web design while documenting my engineering work.
SystemVerilog autonomous controller using a Zynq-7000 SoC, ultrasonic sensing, infrared boundary detection, PWM motor control, and finite-state-machine navigation.
Mixed-signal PCB development, hardware bring-up, signal validation, troubleshooting, and cost-reduction work for a ballistocardiogram (BCG) data-acquisition platform.