256-Bit Matrix Soft Processor

This project implements a soft processor in SystemVerilog with separate instruction memory, main memory, matrix ALU, integer ALU, execution engine, and simulation modules. Every component communicates through one address-decoded, 256-bit tri-state bus.

The wide datapath is the defining architectural choice: all sixteen elements of a 4 × 4 matrix fit in a single word. The execution engine controls which module owns the bus, sequences each transfer, and routes completed results back to memory or its internal registers.

The upper address nibble selects a processor module, while lower address bits select a local memory location or register. A selected source drives the bus; all other modules remain in a high-impedance state until the controller authorizes them to transmit.

Each 32-bit instruction identifies an opcode, destination, and two operand sources. The controller fetches and decodes the instruction, moves each operand to the selected ALU, starts the operation, waits for its result, and writes that result to its destination before fetching the next instruction.

Matrix opcodes are routed to the matrix ALU, while opcodes beginning with hexadecimal 1 select the integer ALU. Opcode 0xFF cleanly stops processor execution and allows the test environment to check results.

Implemented matrix operations

• 4 × 4 matrix multiplication
• Element-by-element addition and subtraction
• Matrix transpose
• Bus-supplied matrix scaling
• Immediate-value matrix scaling

Integer operations

The integer ALU supports addition, subtraction, multiplication, and division. Its operands and result use the same 256-bit transfer path, allowing both compute units to share the memory and control system.

The included program exercises matrix addition, scaling, subtraction, transpose and multiplication, as well as all four integer operations and transfers through internal registers.

• Generates a reset pulse and a 10 ns simulation clock.
• Exercises matrix, integer, memory, and internal-register operations.
• Stops execution when the processor decodes opcode 0xFF.
• Compares final memory and register values against expected results.
• Reports a passing memory check after the complete instruction sequence.

• Application-specific processor architecture and instruction design.
• Address decoding and coordinated ownership of a shared tri-state bus.
• Finite-state-machine control of multi-cycle data movement and execution.
• Parallel representation and processing of complete 4 × 4 matrices.
• Integration of independent memory, control, and arithmetic modules.
• Self-checking behavioral simulation in AMD Vivado and XSim.