404: Bot Not Found

404: Bot Not Found was an eight-person senior design project centered on developing a reusable FPGA learning platform for Texas State University’s Digital Systems Using HDL course.

The platform was built around the Digilent Cora Z7, which combines Zynq-7000 programmable logic with an ARM processing system. This architecture allowed students to study HDL development, embedded programming, AXI communication, peripheral integration, simulation, and hardware verification in one environment.

The system integrated GPIO, SPI, I2C, and PWM peripherals through an AXI-based architecture. These interfaces connected the Cora Z7 to external sensors, OLED displays, LEDs, motor-control hardware, and a custom peripheral PCB.

Testbenches, embedded applications, bitstream releases, hardware platforms, test procedures, and technical documentation were developed alongside the hardware so that future students could reproduce, study, and expand the system.

The project addressed the gap between learning HDL syntax in a classroom and developing a complete FPGA-based system. Students could follow a practical engineering workflow: create digital logic, simulate its behavior, integrate IP, build the design, deploy it to hardware, and verify the result.

The platform also demonstrated the relationship between software and programmable hardware. Embedded C applications running on the ARM processor accessed AXI-connected peripherals implemented in the FPGA fabric, allowing students to see how firmware and digital logic work together.

Instead of presenting the system only as a finished demonstration, the project provided reusable hardware, software, verification examples, and instructional documentation that could support future laboratory exercises.

The platform used the dual architecture of the Zynq-7000 SoC. The ARM processing system handled embedded software and high-level control, while the programmable logic contained AXI-connected peripheral interfaces and custom hardware.

AXI SmartConnect provided memory-mapped communication between the processing system and programmable-logic peripherals. The complete platform connected these interfaces to displays, sensors, LEDs, buttons, motor drivers, DC motors, and a custom PCB.

The Vivado block design brought together the Zynq processing system, AXI SmartConnect, processor resets, AXI Verification IP, GPIO interfaces, SPI controllers, an I2C controller, and custom PWM peripherals.

Each peripheral was assigned a memory address that allowed embedded software and testbench transactions to access its control and status registers. As the individual subsystem designs changed, the master hardware platform had to be updated and rebuilt while preserving clocking, reset behavior, address mapping, and external pin routing.

The completed project extended beyond a single FPGA design. It included the hardware platform, embedded applications, physical peripherals, simulation tools, deployment files, and instructional resources required to reproduce and understand the system.

I served as the project manager while also owning the master FPGA hardware-platform integration and deployment workflow. My technical responsibility was to maintain the Vivado design that brought the team’s peripheral subsystems together into a deployable Zynq-7000 configuration.

As subsystem requirements evolved, I incorporated the necessary AXI IP blocks, validated connections and address assignments, ran synthesis and implementation, generated the FPGA bitstream, and exported the XSA hardware platform used by the embedded-software team.

I maintained and distributed matching hardware releases so the bitstream, block design, XSA platform, testbench environment, and embedded applications remained aligned across project revisions.

I also assisted with the HDL verification effort by helping develop, execute, and debug AXI VIP simulations for the GPIO, PWM, SPI, and I2C peripherals. This work helped confirm register-level communication and peripheral behavior before physical deployment.

• Served as project manager for an eight-person engineering team.
• Owned the master Vivado block design and XSA hardware-platform iterations.
• Integrated AXI-connected GPIO, SPI, I2C, and PWM peripherals into the Zynq-7000 design.
• Generated, versioned, validated, and deployed FPGA bitstream and XSA releases.
• Maintained reproducible hardware configurations as subsystem requirements changed.
• Assisted with AXI VIP testbench development and simulation for GPIO, PWM, SPI, and I2C.
• Supported synthesis, implementation, hardware validation, and system-level debugging.
• Designed the autonomous robot chassis and mechanical assembly in SolidWorks as an independent project extension.

Verification was performed at multiple levels. Individual peripherals were first exercised through simulation and register transactions before being validated through embedded software and physical hardware.

The testbench environment instantiated the Cora Z7 design wrapper and used AXI Verification IP as the master interface. AXI VIP generated register transactions through AXI SmartConnect to exercise the memory-mapped GPIO, SPI, I2C, and PWM peripherals.

Hardware validation confirmed address mapping, register behavior, signal routing, and communication with external devices. Oscilloscopes and logic analyzers were used to inspect signals and troubleshoot timing, interface, and integration problems.

• Vivado block-design validation
• Synthesis, implementation, and bitstream generation
• XSA hardware-platform generation and deployment
• SystemVerilog simulation using XSim
• AXI VIP register transactions and protocol verification
• GPIO, SPI, I2C, and PWM peripheral testing
• ARM-to-programmable-logic communication testing
• Oscilloscope and logic-analyzer measurements
• Fabric-clock performance characterization
• Full-system hardware integration testing

I generated and tested multiple hardware-platform revisions using different programmable-logic fabric-clock frequencies. Peripheral operation and simulation were evaluated at 25, 100, 150, 200, and 250 MHz.

The platform’s communication interfaces operated successfully at 25, 100, and 150 MHz. At 200 and 250 MHz, SPI communication failed while I2C and the other interfaces continued to operate. The results identified a practical limitation involving the fabric clock, SPI divider configuration, and connected peripheral requirements.

Outside the core team deliverables, I continued developing the platform as an autonomous robot. This extension demonstrated how the same HDL, peripheral, verification, and hardware-integration concepts could be applied to a complete physical system.

I designed the robot chassis and mechanical assembly in SolidWorks. The three-level structure organized the motors, batteries, sensors, Cora Z7, and project electronics while protecting the hardware and maintaining access for testing and development.

The lower level supported the drive system and boundary sensors, the middle level housed the batteries, and the upper level supported the FPGA board, electronics, and ranging sensors.

The project produced a working Zynq-7000 hardware platform with AXI-connected GPIO, SPI, I2C, and PWM peripherals, embedded applications, simulation testbenches, a custom PCB, and documented operating and testing procedures.

The platform demonstrated a repeatable workflow from HDL and IP integration through simulation, bitstream generation, XSA export, embedded-software integration, and physical hardware validation.

The autonomous-robot extension provided a path for applying the educational platform to sensing, motor control, safety logic, mechanical design, and real-time physical behavior.

The project was recognized by visiting industry professionals as the top capstone project presented at the senior design showcase.